/*----------------------------------------------------------------------------
 * Copyright (c) <2013-2015>, <Huawei Technologies Co., Ltd>
 * All rights reserved.
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 * 1. Redistributions of source code must retain the above copyright notice, this list of
 * conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright notice, this list
 * of conditions and the following disclaimer in the documentation and/or other materials
 * provided with the distribution.
 * 3. Neither the name of the copyright holder nor the names of its contributors may be used
 * to endorse or promote products derived from this software without specific prior written
 * permission.
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *---------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
 * Notice of Export Control Law
 * ===============================================
 * Huawei LiteOS may be subject to applicable export control laws and regulations, which might
 * include those applicable to Huawei LiteOS of U.S. and the country in which you are located.
 * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such
 * applicable export control laws and regulations.
 *---------------------------------------------------------------------------*/
#ifndef __HISOC_MMC_H_
#define __HISOC_MMC_H_

/************************************************************************/

#include "asm/platform.h"
#include "mmc/mmc_os_adapt.h"
#include "mmc/host.h"
#include "sdhci/sdhci_reg.h"
#include "sdhci/sdhci.h"

#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */

/************************************************************************/

#define MAX_MMC_NUM    2
#define USE_MMC0 1
#define USE_MMC1 1

#define MMC0    0
#define MMC1    1

//sdio0 & emmc
#define CONFIG_MMC0_CCLK_MIN    100000     //100KHz
#define CONFIG_MMC0_CCLK_MAX    150000000  //200MHz

//sdio1
#define CONFIG_MMC1_CCLK_MIN    100000     //100KHz
#define CONFIG_MMC1_CCLK_MAX    50000000   //200MHz


///// not exist
#define PERI_CRG86              (CRG_REG_BASE + 0x158)
#define PERI_CRG87              (CRG_REG_BASE + 0x15C)
#define PERI_CRG94              (CRG_REG_BASE + 0x178)
#define PERI_CRG95              (CRG_REG_BASE + 0x17C)
#define PERI_CRG96              (CRG_REG_BASE + 0x180)

#define PERI_CRG106             (CRG_REG_BASE + 0x1A8)
#define PERI_CRG117             (CRG_REG_BASE + 0x01D4)
#define PERI_CRG123             (CRG_REG_BASE + 0x1EC)
#define PERI_CRG133             (CRG_REG_BASE + 0x214)
#define PERI_CRG143             (CRG_REG_BASE + 0x23C)
//////

#define PERI_CRG125 (CRG_REG_BASE + 0x01F4)

//eMMC DRV DLL
#define PERI_CRG127 (CRG_REG_BASE + 0x01FC)
#define PERI_SAM_DRV_SHFT (24)
#define PERI_SAM_DRV_MASK (0x1f << 24)

//SDIO1 DRV DLL
#define PERI_CRG136 (CRG_REG_BASE + 0x0220)
#define PERI_CRG139 (CRG_REG_BASE + 0x022C)

#define PERI_SDIO0_SAMPLB_DLL_CTRL   (CRG_REG_BASE + 0x1f8)
#define PERI_SDIO1_SAMPLB_DLL_CTRL   (CRG_REG_BASE + 0x21c)
#define SDIO_SAMPLB_DLL_CLK_MASK    (0x1f << 0)
#define SDIO_SAMPLB_SEL(phase)      ((phase) << 0)

#define PERI_SDIO0_DRV_DLL_CTRL   (CRG_REG_BASE + 0x210)
#define PERI_SDIO1_DRV_DLL_CTRL   (CRG_REG_BASE + 0x228)

#define SDIO_DRV_DLL_LOCK       (1<<15)

#define PERI_SDIO0_SAMPL_DLL_STATUS   (CRG_REG_BASE + 0x208)
#define PERI_SDIO1_SAMPL_DLL_STATUS   (CRG_REG_BASE + 0x224)

#define SDIO_SAMPL_DLL_SLAVE_READY  (1)
#define SDIO_SAMPL_DLL_SLAVE_EN     (1<<16)

#define PERI_CRG106_EMMC_CRG_REQ (1U<<27)
#define PERI_CRG106_EMMC_CKEN (1U<<28)
#define PERI_CRG106_EMMC_DLL_RST (1U<<29)
#define PERI_CRG106_EMMC_SAM_RST (1U<<30)

#define EMMC_PHY_BASE           0x12160000

#define MMC_FREQ_100K       100000
#define MMC_FREQ_400K       400000
#define MMC_FREQ_25M        25000000
#define MMC_FREQ_50M        50000000
//only support for EMMC chip
#define MMC_FREQ_90M        90000000
#define MMC_FREQ_112P5M     112500000
#define MMC_FREQ_150M       150000000


#define MMC_FREQ_MASK       0x7
#define MMC_FREQ_SHIFT      24
#define SDIO0_CKEN          (1<<28)
#define SDIO0_CLK_SEL_100K  (0)
#define SDIO0_CLK_SEL_400K  (7)
#define SDIO0_CLK_SEL_25M   (1)
#define SDIO0_CLK_SEL_50M   (2)
#define SDIO0_CLK_SEL_100M  (3)
#define SDIO0_CLK_SEL_125M  (4)
#define SDIO0_CLK_SEL_150M  (5)
#define SDIO0_CLK_SEL_200M  (6)


#define REG_CTRL_BASE (0x100C0040)

#define REG_CTRL_SDIO0_CLK      (0x100C0040)
#define REG_CTRL_SDIO0_CMD      (0x100C0044)
#define REG_CTRL_SDIO0_DATA0    (0x100C0048)
#define REG_CTRL_SDIO0_DATA1    (0x100C004C)
#define REG_CTRL_SDIO0_DATA2    (0x100C0050)
#define REG_CTRL_SDIO0_DATA3    (0x100C0054)

#define REG_CTRL_SDIO0_CD_DET (0x100C005C)

#define REG_CTRL_SDIO0_CD_POW (0x120C0020)

#define REG_CTRL_SDIO1_CLK      (0x112c0048)
#define REG_CTRL_SDIO1_CMD      (0x112c004c)
#define REG_CTRL_SDIO1_DATA0    (0x112c0064)
#define REG_CTRL_SDIO1_DATA1    (0x112c0060)
#define REG_CTRL_SDIO1_DATA2    (0x112c005c)
#define REG_CTRL_SDIO1_DATA3    (0x112c0058)

#define REG_CTRL_EMMC_CLK    (0x100C0014)
#define REG_CTRL_EMMC_CMD    (0x100C0018)
#define REG_CTRL_EMMC_DATA0  (0x100C0020)
#define REG_CTRL_EMMC_DATA1  (0x100C001c)
#define REG_CTRL_EMMC_DATA2  (0x100C0028)
#define REG_CTRL_EMMC_DATA3  (0x100C0024)
#define REG_CTRL_EMMC_DATA4  (0x100C0030)
#define REG_CTRL_EMMC_DATA5  (0x100C0034)
#define REG_CTRL_EMMC_DATA6  (0x100C0038)
#define REG_CTRL_EMMC_DATA7  (0x100C003c)

#define REG_CTRL_EMMC_DS     (0x100C0058)
#define REG_CTRL_EMMC_RST    (0x100C005C)

// macro for io_mux
#define IO_CFG_SR               BIT(10)
#define IO_CFG_PULL_DOWN        BIT(9)
#define IO_CFG_PULL_UP          BIT(8)
#define IO_CFG_DRV_STR_MASK     (0xf << 4)
#define IO_DRV_MASK             (0x7f0)

#define IO_DRV_STR_SEL(str)     ((str) << 4)

#define IO_MUX_CLK_TYPE_EMMC    0x0
#define IO_MUX_CLK_TYPE_SD      0x1
#define IO_MUX_SHIFT(type)      ((type) << 0)
#define IO_MUX_MASK             (0xf << 0)

#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif

